NXP Semiconductors /MIMXRT1011 /LPSPI1 /CFGR0

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Interpret as CFGR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HREN_0)HREN 0 (HRPOL_0)HRPOL 0 (HRSEL_0)HRSEL 0 (CIRFIFO_0)CIRFIFO 0 (RDMO_0)RDMO

RDMO=RDMO_0, CIRFIFO=CIRFIFO_0, HREN=HREN_0, HRSEL=HRSEL_0, HRPOL=HRPOL_0

Description

Configuration Register 0

Fields

HREN

Host Request Enable

0 (HREN_0): Host request is disabled

1 (HREN_1): Host request is enabled

HRPOL

Host Request Polarity

0 (HRPOL_0): Active low

1 (HRPOL_1): Active high

HRSEL

Host Request Select

0 (HRSEL_0): Host request input is the LPSPI_HREQ pin

1 (HRSEL_1): Host request input is the input trigger

CIRFIFO

Circular FIFO Enable

0 (CIRFIFO_0): Circular FIFO is disabled

1 (CIRFIFO_1): Circular FIFO is enabled

RDMO

Receive Data Match Only

0 (RDMO_0): Received data is stored in the receive FIFO as in normal operations

1 (RDMO_1): Received data is discarded unless the Data Match Flag (DMF) is set

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